发明名称 |
Switched substrate bias for logic circuits |
摘要 |
A semiconductor circuit or a MOS-DRAM wherein converting means is provided that converts substrate potential or body bias potential between two values for MOS-FETs in a logic circuit, memory cells, and operating circuit of the MOS-DRAM, thereby raising the threshold voltage of the MOS-FETs when in the standby state and lowering it when in active state. The converting means includes a level shift circuit and a switch circuit. The substrate potential or body bias potential is controlled only of the MOS-FETs which are nonconducting in the standby state; this configuration achieves a reduction in power consumption associated with the potential switching. Furthermore, in a structure where MOS-FETs of the same conductivity type are formed adjacent to each other, MOS-FETs of SOI structure are preferable for better results.
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申请公布号 |
US5610533(A) |
申请公布日期 |
1997.03.11 |
申请号 |
US19940350064 |
申请日期 |
1994.11.29 |
申请人 |
MITSUBISHI DENKI KABUSHIKI KAISHA |
发明人 |
ARIMOTO, KAZUTAMI;TSUKUDE, MASAKI |
分类号 |
H01L27/02;H01L27/12;H03K19/00;(IPC1-7):H03K17/16 |
主分类号 |
H01L27/02 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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