发明名称 METHOD FOR ARRANGING AND WIRING FLIP-CHIP-TYPE SEMICONDUCTOR DEVICE
摘要 PROBLEM TO BE SOLVED: To easily automate the ASIC design in flip-chip configuration by increasing the degree of freedom of the arrangement of input/output buffers without affecting the basic algorithm of an automatic arrangement wiring tool used for a conventional ASIC design. SOLUTION: The arrangement position of an input/output buffer arrangement part and that of an internal circuit arrangement part are commonly defined without any distinction (processes 11-15). On the other hand, input/output buffers are arranged in one row (processes 17-18) and the power supply to them is separated into a plurality of electrically independent systems as needed so that they can be constantly kept (process 19), thus arranging the input/output buffers with an extremely high degree of freedom in a conventional automatic arrangement wiring program, extremely reducing the free region in a chip which is generated before, increasing the degree of chip designing freedom in terms of characteristics and performance including various environments on a packaging board, and further extremely easily connecting a power supply wiring to the input/output buffers.
申请公布号 JPH0969568(A) 申请公布日期 1997.03.11
申请号 JP19950222290 申请日期 1995.08.30
申请人 NEC CORP 发明人 ITO SOICHI
分类号 H01L27/04;G06F17/50;H01L21/82;H01L21/822 主分类号 H01L27/04
代理机构 代理人
主权项
地址