| 摘要 |
A failure analyzer for the semiconductor tester which tests a plurality of devices at the same time and stores a first fail information for each device under test (DUT) and inhibits further fail information from being stored in a fail memory. The failure analyzer includes a plurality of comparators connected to corresponding DUT for generating a fail signal when the output signal from the DUT disagrees with an expected signal, a fail memory connected to the comparators to store fail information on the DUT, a plurality of fail receiving circuits for receiving the fail signals from the comparators wherein each of the fail receiving circuits counts the number of the fail signal from corresponding one of the comparators and generating a counted signal when the fail signal reaches a predetermined number, a plurality of inhibit circuits connected to the fail receiving circuits to inhibit the fail signals received after the predetermined number from affecting the fail memory, an OR-gate for combining output signals from the inhibit circuits to generate an overall fail signal, and a fail memory controller connected to the fail memory to enable the fail memory when receiving the overall fail signal from the OR-gate.
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