发明名称 Semiconductor memory device having a hierarchical bit line structure with reduced interference noise
摘要 Bit lines includes sub-bit lines arranged corresponding to respective memory cell column groups, and also includes main bit lines MBLa and MBLb. When selecting a word line, a separation transistor is turned off, so that the main bit line is divided into two divided main bit lines, and a memory group including the selected word line and a memory cell block which is disposed at a symmetrical position with respect to the separation transistor are selected. After the separation transistor is turned off, sense amplifiers perform sensing operation. Influence against the sensing operation, which may be caused by noises due to a bit line capacitance, is prevented, and the hierarchical bit lines are accurately equalized and precharged.
申请公布号 US5610871(A) 申请公布日期 1997.03.11
申请号 US19940341145 申请日期 1994.11.16
申请人 MITSUBISHI DENKI KABUSHIKI KAISHA 发明人 HIDAKA, HIDETO
分类号 G11C11/401;G11C5/06;G11C7/18;G11C11/409;(IPC1-7):G11C8/00 主分类号 G11C11/401
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