| 摘要 |
PROBLEM TO BE SOLVED: To reduce the number of required set-up of sub-word line drive circuits such as dynamic RAM, etc., taking a hierarchical word line structure and to reduce a cost and power consumption. SOLUTION: This storage is a dynamic RAM, etc., provided with an X address decoder XD taking the hierarchical word line structure and selectively making a main word line a selection level and plural sub-memory arrays SM arranged in the prolonging direction of the main word line. The number of bit lines of the sub-memory arrays SML00-SML17 and SMR00-SMR17 arranged on the X address decoder near end side of the main word line are doubled compared with the sub-memory arrays SML20-SML57 and SMR20-SMR57 arranged on the far end side. Thus, the number of set-up of bit lines are increased matching with sub-word line selection timing margins of respective sub-memory arrays, and the number of required set-up of the sub-memory arrays, that is, sub-word line drive circuits WDR are reduced. |
