NONVOLATILE SEMICONDUCTOR MEMORY DEVICE

摘要

PROBLEM TO BE SOLVED: To prevent the content of cells from over erasion by performing an erasing operation only when data of all memory cells become zero and stopping the judgement of data during erasion and an erasion verifying mode sequence. SOLUTION: When all zero verifying signals 22 outputted by an over erasion preventing circuit 20 become high level, sense amplifiers 13a-13h are activated. All zero verifying fail signals 19 are generated by the theoretical sum of the value of respective amplifier outputting lines 14a-14h in an all zero judging circuit 18 and become low level when all memory cells become zero data. Both all zero verifying signals 22 and erasing timer signals 4 are subjected to be low level at the time of the usual operation in a Y decoder. Only one line output in the Y decoder 17 is subjected to be high level by outputs of positive theoretical signal lines 43-45 and negative theoretical signal lines 46-48. Over erasion is prevented by allowing to perform the erasing operation only when all outputs of the Y decoder 17 are specified to be low level and all memory cells are specified to be zero data.