| 摘要 |
PROBLEM TO BE SOLVED: To provide a semiconductor memory device and manufacture thereof enabling miniaturization of a shared contact forming region, without increasing the contact resistance. SOLUTION: A polycrystalline Si layer 40 is additionally provided and simultaneously connected to both a gate electrode (polycide layer 27) of an NMOS transistor 14 and source-drain region (N<-> type impurity region 29 and N<+> type impurity region 36) of an NMOS transistor 13. Contact openings 46 are formed through interlayer insulation films (Si oxide films 44 and 45) to the layer 40 and a gate electrode layer (polycrystalline Si layer 47) of a TFT 15 is formed so as to cover the openings 46 whereby the gate electrodes of the TFT 15 contact only with the Si layer 40 and its horizontal contact distance is equal to the size d of the opening 46. If the size of the opening 46 is reduced more than that in the prior art, the contact area can be enough ensured and the contact resistance does not increase. |
