| 摘要 |
<p>PROBLEM TO BE SOLVED: To early detect an error by feeding back an output of a shift register with the same length as a data unit and connecting in parallel with a divider to a specific register input of the divider detecting a cyclic redundancy code error. SOLUTION: A cyclic redundancy code CRC check section 6 has a shift register 1 latching data by 1 multi-frame (in 3156 bits), a decoder 2 to detect a frame bit pattern, a feedback type shift register 3 (divider) for CRC error check. A desired divider output is obtained by adding an output of a final stage of the shift register 1 to each input of 1st to 5th stage of the divider with an exclusive OR 7. CRC error scanning is applied to the latest 3156 bit at all times, for example, by conducting sequentially the processing for each input of 1-bit. Thus, a useless time of restoring to a hunting state after 1 multi- frame is omitted and a time up to synchronization establishment is reduced.</p> |
