| 摘要 |
PROBLEM TO BE SOLVED: To increase channel width as compared with the conventional one, by constituting first and second selection transistors of at least one side so that the current directions in the channel parts are the second direction and the gate width is greater than the widths of first and second digit lines. SOLUTION: N<+> diffusion layer parts MDO1 , MDO2 , SDO1 , SDO2 corresponding to the source and the drain of a MOS transistor for block selection are made longer than the lengths in the word line direction of the diffusion layers of width digit lines SD1 , SD3 . N<+> diffusion layer parts MDE1 , MDE2 , SDE1 , SDE2 corresponding to the source and the drain of the MOS transistor for block selection are made longer than the lengths in the word line direction of the diffusion layers of width digit lines SD2 , SD4 . By adopting the above layout, the channel width can be increased as compared with the conventional one, while the increase of chip area and capacitance is restrained. |
