| 摘要 |
PROBLEM TO BE SOLVED: To reduce the number of manufacturing processes of a DRAM having a memory cell of a capacitor-over-bit-line structure, and reduce the difference in aspect ratios of a contact hole formed in a region of the memory cell and a contact hole formed in a region of a peripheral circuit. SOLUTION: Wirings 20, 21 of a first layer of a peripheral circuit and an upper electrode 19 of a capacitive element for storing information of a memory cell are simultaneously formed by using wiring material of the same layer. A wiring 27 of a second layer of the peripheral circuit and a wiring 25 on the upper electrode 19 are simultaneously formed by using wiring material of the same layer. |
