发明名称 SDH SYNCHRONOUS COMMUNICATION EQUIPMENT
摘要 PROBLEM TO BE SOLVED: To simplify the configuration and the operation by controlling the selection as to whether an S1 byte separated from an STM-N signal or an S1 byte corresponding to the quality of an in-equipment synchronization clock is multiplexed. SOLUTION: In the case of synchronous communication, an S1 byte selector 106a of a control circuit 104a selects an S1 byte obtained by converting a quality level 14 from a clock quality monitor circuit 105a and gives the selected byte to an SOH multiplex circuit 103a. The circuit 103a multiplexes a pointer generated by a clock signal selected by the circuit 105a and the S1 byte. In the case of adopting the subordinate synchronization system, a selector 106b of a control circuit 104b is controlled to output the S1 byte extracted by an SOH separate circuit 101b to an SOH multiplex circuit without any modification and the operation of a quality monitor circuit is omitted. A pointer generated by the line extract clock and the S1 byte are multiplexed by the circuit 103b in this channel.
申请公布号 JPH0964842(A) 申请公布日期 1997.03.07
申请号 JP19950211448 申请日期 1995.08.21
申请人 NEC CORP 发明人 OKABAYASHI TETSUYA
分类号 H04J3/00;H04J3/06;H04L7/00;H04L7/08 主分类号 H04J3/00
代理机构 代理人
主权项
地址