| 摘要 |
PROBLEM TO BE SOLVED: To provide a digital filter in which the circuit configuration is held to the absolute minimum and filtering process is conducted for band limit. SOLUTION: Multipliers 11-13 receive selection data SD in common respectively and multiply coefficients h2, h1, h0 latched by coefficient latch sections 21-23 with the selection data SD to obtain multiplication results SL1-SL3. The result of multiplication SLi (i=1-3) is a multiplication result ML1i based on I data when a selection signal Csel is at 'H' (1st period) and the result of multiplication SLi (i=1-3) is a multiplication result ML2i based on Q data when a selection signal Csel is at 'L' (2nd period), then the ML11 and the ML21 are captured by registers R1, R2 corresponding to the multiplier 11, respectively. Then the ML12 and the ML22 are captured by registers R1, R2 corresponding to the multiplier 12 respectively and the ML13 and the ML23 are captured by registers R1, R2 corresponding to the multiplier 13, respectively. |
