OFF-STATE GATE-OXIDE FIELD REDUCTION IN CMOS

摘要

A MOSFET device utilizes the gate depletion effect to reduce the oxide field over the junction area. Since the gate depletion effect is present in the non-conducting off state for n+ gate PMOS devices and p+ gate NMOS devices, performance degradation is overcome. The level of doping of the gate is critical. In order to prevent gate depletion in the conducting, on state, the NMOS FET must use a highly doped n+ gate. The PMOS FET n+ gate must be non-degeneratively doped in order to utilize the advantage of the gate depletion in the non-conducting, off state. This is accomplished by implanting different doses of the same dopant type into the different gates. The MOSFET device can be implemented equally well for n+ gate PMOS FET devices as well as for p+ gate NMOS FET devices.