| 摘要 |
<p>The gate of a P-channel pull-up transistor (MP1) connected between an input node (A) and a supply voltage (VDD) in a buffer circuit (21) is coupled to a test node (22). An N-channel pull-down transistor (MNpd) is connected between the input node (A) and ground and has a gate connected to the test node (22). A logic low signal provided to the test node (22) allows the circuit (21) to operate normally. During test mode, a logic high signal is provided to the test node (22) to turn off the P-channel pull-up transistor (MP1) and thus prevent DC current flow in the circuit via the pull-up transistor (MP1). This logic high signal also turns on the pull-down transistor (MNpd) and, by shorting the input node (A) to ground potential, prevents any other DC crossover currents from flowing in the circuit (21).</p> |
