| 摘要 |
<p>A current memory comprises an input (1) which is connected via a switch (S1) which is closed on a phase ζ1 of a clock signal to inputs of a coarse memory cell (M1) and a fine memory cell (M2). The coarse memory cell samples the input current on phase ζ1a of the clock and outputs a current thereafter. The fine memory cell senses the difference between the input current and the output of the coarse memory (M1) on phase ζ1b of the clock. A switch (S2) which is closed on phase ζ2 of the clock passes the combined outputs of the coarse (M1) and fine (M2) memories to an output 3. Two further switches (S6, S7) are provided which are closed for a short time (sh1) at the start of phase ζ1b. These serve to discharge the stray capacitance (Cn) at the node (2) to the voltage reference source via terminal 4.</p> |
