| 摘要 |
A current memory for balanced current inputs comprises two coarse (M1, M11) and two fine (M2, M12) current memory cells each of which comprises a field effect transistor (T1, T11, T2, T12) having a switch (S3, S13, S4, S14) between its gate and source electrodes. Parasitic gate-drain capacitances (C3, C13, C4, C14) are neutralised by capacitors (C31-C34) connected between the gate and drain electrodes of opposite pairs of transistors. Other current transport errors can be compensated by providing appropriately dimensioned extra capacitance added to each of the neutralising capacitors (C31-C34). |
