PIXEL ENGINE PIPELINE FOR A 3D GRAPHICS ACCELERATOR

摘要

A pixel engine pipeline, including a "front-end" and a "back-end", communicates pixel information between a graphics processor (110), a data cache (135), and system memory (170). The front-end (for reading request data) includes a commande queue (210) for receiving graphics instructions from the graphics processor (110). Requested data from the command queue (210) is provided to a stage of the pixel engine (120) from the read data queue (230). The back-end (for writing graphics information to system memory) of the pixel engine pipeline includes a write data queue (310) receiving write data from the pixel engine (120), wherein the write data includes pixel information interleaved with Z information. A multiplexer (330) selects a selected buffer from one of a pair of buffers (320) containing pixel information and Z information, respectively. The selected buffer is written to a store buffer for subsequent writing to system memory (170).