| 摘要 |
The unit has a fault memory, for storing fault data related to the memory to be tested, under an address, selected by address data from a memory test system, if a fault signal is produced by a logical comparator in the memory test system. An OR circuit prepares input data for the fault storage on the basis of an OR logical linking, between the fault signal from the logical comparator and data, which is stored in the fault storage, under an address selected by the address data. A recording release control (24) produces a recording release signal, which is to be supplied to the fault storage on the basis of the fault signals from the logical comparator. An AND circuit is fed with the fault signal from the comparator and with the data, which is stored in the data memory, under an address selected by the address data, in order to transmit the fault signal, if the data from the fault storage indicates that the fault data under the address is not yet stored. A fault counter (23) counts the number of fault signals, which are transmitted from the AND circuit in the course of a test of the storage to be tested, by the semiconductor storage test system.
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