| 摘要 |
<p>PROBLEM TO BE SOLVED: To obtain a failure diagnostic apparatus by which the failure diagnostic accuracy of a large-scale memory macrocell can be improved by installing a means by which a connection circuit between leaf cells for a function cell and a transistor circuit inside a cell are extracted from layout data and a means by which a transistor is replaced by a logic simulation model. SOLUTION: A transistor net list inside a cell extracted by an inside-cell circuit extraction part 30 is stored in a storage means 44 as a logic simulation model by a transistor conversion processing part 41, a logic-leaf-cell conversion processing part 42 and an analog-leaf-cell conversion processing part 43. In this manner, a model is added to a cell logic simulation model 12 used on the side of a cell logic simulation, and it is used for a logic simulation. In addition, when the logic simulation model in the case of a failure inside a leaf cell is added to an intercell circuit A11 and an intercell circuit B22, it is possible to deal with the layout of a circuit inside a leaf cell, and a failure inside the leaf cell can be tracked.</p> |
