Semiconductor memory device allowing data rewriting electrically

摘要

A memory array block MK of the same structure is arranged in all the memory array regions MA of a DRAM. An IO line control circuit connects the other end of a pair of local signal input/output lines to one end of a pair of global signal input/output lines in an opposite phase or a positive phase in response to one end of the corresponding pair of local signal input/output lines being connected to an even numbered bit line pair of the upper row of memory array region MA or an odd numbered bit line pair of the lower row of memory array region MA. Since the memory array blocks MK in all the memory array region MA have the same structure, a memory cell corresponding to a defective address detected in a BI test can easily be identified.