INTERRUPTED CLOCK DETECTING CIRCUIT

摘要

PROBLEM TO BE SOLVED: To enable interrupted clock detection with a small circuit scale and low power consumption by one basic circuit irrelevantly to whether a clock is at a high or low level. SOLUTION: A clock input terminal 3 is connected to the gate of a P channel TR 10 through the gate of a P channel MOS transistor (TR)1 and an inverter 12. The source of the P channel MOS TR 10 is connected to a power source 5, a capacitor 11 is connected between its drain and the source of the P channel MOS TR 1, and capacitor 6 is connected between the drain of the P channel MOS TR 1 and the drain of an N channel MOS TR 2. To the capacitor 6, a compactor 7 which has one input terminal connected to a reference voltage 8 is connected at the other input terminal. When the clock stops at the high level or low level, P channel MOS TRs 1 and 10 turn off and the voltage to the other input terminal of the compactor 7 becomes lower than the reference voltage 8, thereby deciding that the clock is ceased.