发明名称 |
Integrated data processing system including CPU core and parallel, independently operating DSP module and having multiple operating modes |
摘要 |
An integrated circuit structure, having a central processing unit (CPU) formed as a part thereof, for configuring the CPU for operating in an operating mode selected from a plurality of possible operating modes. The possible operating modes include a first possible operating mode that operates exclusively on internal memory storage elements, a second possible operating mode that operates exclusively on external memory storage elements via an external bus connected to a first portion of a plurality of general purpose I/O pins, and a third possible operating mode that operates on external memory storage elements via an external bus connected to a second portion of the general purpose I/O pins such that additional external I/O circuitry is necessary to handle I/O transfers.
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申请公布号 |
US5606714(A) |
申请公布日期 |
1997.02.25 |
申请号 |
US19950566254 |
申请日期 |
1995.12.01 |
申请人 |
NATIONAL SEMICONDUCTOR CORPORATION |
发明人 |
INTRATER, GIDEON;DORON, MOSHE;EPSTEIN, LEV |
分类号 |
G06F9/32;G06F9/38;G06F11/36;G06F13/24;G06F15/78;H04L27/38;(IPC1-7):G06F13/00 |
主分类号 |
G06F9/32 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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