| 摘要 |
A memory device 72 is provided which includes a plurality of data storage locations each having an associated address and arranged as a plurality of planes 76. A data port 78, 86 is coupled to each of the planes 76. Control circuitry 78, 80, 82 is provided and includes inputs receiving an address and a mode control signal, the control circuitry operable in the first mode to provide access through data port 78, 86 to an addressed location in each of the plurality of planes 76 and in a second mode to provide access through the data port 78, 86 to a plurality of storage locations in a selected one of the planes 76.
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