发明名称 SIGNAL PROCESSOR
摘要 PROBLEM TO BE SOLVED: To surely carry out the tasks which are scheduled among control processors in a correct sequence by automatically scheduling the control task of a single control processor or the control tasks of plural control processors in plural time slices. SOLUTION: Every control processor 16P is connected to a common control line 72 to which a 1-bit register 70 is connected. When one of processors 16P starts a task to a new time slice, the processor 16P writes a busy signal (e.g. binary '1') into the line 72 and keeps the busy signal until the end of the time slice. When the time slice ends, the inverse binary value (e.g. binary '0') is written into the line 72. When the final processor 16P writes the inverse binary value, the task of every processor 16P is discontinued. Thus it is shown that all processors 16P finishes the tasks concerning the time slices. In this state only, every processor 16P starts the next time slice.
申请公布号 JPH0954760(A) 申请公布日期 1997.02.25
申请号 JP19960161982 申请日期 1996.06.21
申请人 SONY UNITED KINGDOM LTD 发明人 PIITAA CHIYAARUZU IISUTEI;UIRIAMU EDOMANDO KURANSUTAN KENTEITSUSHIYU;KURISUTOFUA MAIKERU MATSUKUROTSUKU
分类号 G06F15/16;G06F15/177;G06T1/20;H03G3/02;H03G9/00;H03H17/00;H03H17/02 主分类号 G06F15/16
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