发明名称 |
INTEGRATED CIRCUIT WITH TEST CIRCUIT AND TESTING METHOD |
摘要 |
PROBLEM TO BE SOLVED: To improve testability by enabling a microprocessor core to be tested with a standard AVP by providing a rest mode matrix circuit which controls the signal transmission route of an integrated circuit device. SOLUTION: A test mode matrix 340 connects a microprocessor core 310, a logic circuit 320 for specific application and an I/O circuit 330 mutually. As a result, the processor core 310 is tested by connecting an external test device to the I/O circuit 330 and using a standard test vector, and the system test and debug of the logic circuit 320 and a code are performed by connecting an ICE to the I/O circuit 330. The test mode matrix 340 performs the required connection of the processor core 310 and the logic circuit 320 without passing any signal through an off-chip driver/receiver and furthermore, without passing through a three-state element, which maintains perfect testability consequently. |
申请公布号 |
JPH0954705(A) |
申请公布日期 |
1997.02.25 |
申请号 |
JP19960136538 |
申请日期 |
1996.05.30 |
申请人 |
INTERNATL BUSINESS MACH CORP <IBM> |
发明人 |
KOOBU ANSERU CHIERICHIETSUTEI;PIITAA SUCHIYUAATO KORIYAA;DEIBITSUDO ROBAATO SUTOOFUAA |
分类号 |
G06F11/22;G01R31/3185;G06F11/267;G06F15/78;H01L23/52 |
主分类号 |
G06F11/22 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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