MULTI-BIT SIGMA-DELTA DAC

摘要

In multi-bit sigma-delta digital-to-analog (D/A) conversion, a highly linear switched-capacitor digital-to-analog converter (17) (DAC) in accordance with the invention is employed. The inventive DAC includes an array of holding capacitors (C12, C11, C21, C22) connected in parallel to an opamp (23) having a finite gain. A conversion period is divided into subintervals and each holding capacitor is associated with one of the subintervals. The inventive DAC also includes switches (S10, S20, S12, S22, S11, S21) for transferring a packet of charge to each holding capacitor during the subinterval associated with the holding capacitor.