| 摘要 |
The equaliser has n frequency regions for digitised signals. A desired amplitude characteristic is set up using n-1 cascaded digital low and high pass filter circuits (F1,F2) whose selection edges define the frequency boundaries between adjacent frequency regions. The n-1 filter circuits each contain a parallel circuit of a low pass (TP) and a high pass (HP) filter, whose frequency characteristics are combined by complementary transfer functions and whose outputs are recombined via a combination stage. A relative amplitude increase or decrease in the direction of increasing frequency occurs between adjacent frequency regions using weighting of the filter output signals. For an increase the high pass filter output is weighted more and for a decrease the low pass filter output is weighted more. The weighting is performed by a controller (st) which forms modified control signals from an input equaliser control signal according to the filter cascading. |
