| 摘要 |
<p>An in-system programming/erasing/verifying structure for non-volatile programmable logic devices includes a data input pin (TDI), a data output pin, an instruction register (103A, 103B), a plurality of data registers (506A, 506B) including an ISP register, wherein said instruction register and said plurality of data registers are coupled in parallel between said data input pin and said data output pin, and a controller for synchronizing said instruction register and said plurality of data registers. The ISP register includes: an address field, a data field, and a status field. An ISP instruction need only be entered once to program/erase the entire device. Specifically, the address/data packets can be shifted back to back into the ISP register without inserting multiple instructions between each packet at the data input pin, thereby dramatically decreasing the time required to program/erase the entire device in comparison to known ISP methods. Furthermore, the invention provides an efficient method for providing the status (i.e. result), of the ISP operations to either the end-user or the supporting software.</p> |
