Semiconductor memory apparatus with a spare memory cell array.

摘要

In a semiconductor memory apparatus having a row decoder classified by main word lines (8) and word lines (28), the number of spare lines for a defect is increased without increasing the number of spare main word lines (22). The area of a redundancy circuit is minimized to improve the yield of chip. Normal and spare memory blocks (50, 52) each including a plurality of memory cells are each divided so that replacement may be effected without increasing the number of spare main word lines even when defective addresses associated with a plurality of normal main word lines take place.