| 摘要 |
PROBLEM TO BE SOLVED: To reduce the circuit area of a constant multiplier which fixes a multiplier and to speed up multiplication. SOLUTION: Logical circuits 31 -3n+2 generates output signals GND, S0 -Sn of one bit by applying different logical operations to an inputted multiplicand of prescribed bits. Multiplication results are outputted to output terminals 41 -4m+1 by supplying the output signals GND, S0 -Sn to the output terminals 41 -4m+1 selectively by an output selection circuit 5 according to a control signal in accordance with the multiplier from an output control circuit 6. |
