发明名称 |
Memory structure with multiple integrated memory array portions |
摘要 |
An integrated memory structure, and associated processing method, is coupled to receive address data and control data. The memory structure includes a composite memory array having a first array portion and a second array portion which are separately addressable. The first array portion is accessed using at least some of the address data as a first address signal and the second array portion is addressed using at least some of the control data also as a second address signal. The memory structure is presented herein by way of example for a serial palette digital-to-analog (SPD) device, and incorporates indirect color mode, direct color mode, overlay color mode and cursor color mode processing in a single macro. When in direct color mode, access to the memory array is disabled and address data is transferred directly to an output of the memory structure as data out.
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申请公布号 |
US5604518(A) |
申请公布日期 |
1997.02.18 |
申请号 |
US19940220090 |
申请日期 |
1994.03.30 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
FLAKER, ROY C.;SCHROER, GREGORY J.;WEST, RODERICK M. P.;WILLIAMS, TODD |
分类号 |
G06F12/00;G09G5/06;G11C5/06;G11C11/401;G11C11/408;(IPC1-7):G09G5/06 |
主分类号 |
G06F12/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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