| 摘要 |
A transition detection device, generating a variable-duration pulse, such as an enable signal for the input circuits of a CMOS static memory circuit, receiving an input signal that includes a delay circuit of determined delay value, making it possible to generate a delayed enable signal, with a safety margin of duration equal to the delay value. A calibration circuit is provided, which includes an exclusive-OR circuit receiving the input signal on a first input. A controlled delay circuit is provided to deliver an input signal delayed by a second delay value to a second input of the exclusive-OR circuit, which, upon access by the CEB signal, delivers a calibrated output pulse of duration equal to the second delay value, and truncated pulses for any transition occurring on the other inputs of the circuit, in the presence of address transitions or of other, not strictly simultaneous, inputs.
|
