| 摘要 |
PROBLEM TO BE SOLVED: To make a timing in the A/D signal conversion in matching with each other at all times by generating a conversion clock for signal conversion synchronously with a timing when a control signal is given to a sample-and-hold circuit. SOLUTION: A conversion block is outputted from a voltage controlled oscillator 3 and fed to an A/D converter 2, frequency-divided by a frequency divider 4 and the result is fed to a phase comparator 5, in which a phase with a control signal is compared. When the phase comparator 5 detects a phase difference and a harmonic being a noise component is cut from the phase difference signal by a low pass filter 6 and the resulting signal is fed to the voltage controlled oscillator 3. Then the voltage controlled oscillator 3 generates newly a conversion clock based on the supplied phase difference and provides an output. The conversion clock outputted from the voltage controlled oscillator 3 is synchronously with the phase of the control signal through a series of feedback operations. |
