| 摘要 |
PROBLEM TO BE SOLVED: To increase the surge resistance of a semiconductor memory by connecting a first well region corresponding to each input terminal to a first upper layer power interconnection only via corresponding lower layer power interconnection. SOLUTION: The n-type well regions NW or power interconnections 1ALVCC of internal protective circuits corresponding to DRAM pads 5.1 to 5.N are not connected by other power interconnections to each other. Accordingly, the interconnection of the protective circuit for the pads 1.4 to 1.M and the interconnection of the protective circuit for pats 5.1 to 5.N are completely the same. Thus, even if a current flows from a resistance element 8 to the interconnection 1ALVCC2, the current does not further flow to the power interconnection 1ALVCC2 corresponding to other pads 5.1, 5.3 to 5.N via the other power interconnection, or does not further flow to the power interconnection 2ALVCC. The current flowing from the element 8 to the interconnection 1ALVCC2 is limited by connecting interconnections 10, 11. |
