| 摘要 |
<p>PROBLEM TO BE SOLVED: To enable execution of writing and erasure for a large number of nonvolatile memory cells by a method wherein different floating gate voltages of a large number of memory cell transistors are converged into a prescribed potential. SOLUTION: A memory cell(MC) array 1 has a plurality of word lines and bit lines and MC is disposed at the position of a point of intersection of each word line and bit line. Floating gates(FG) Ma1 and Mb1 have sources or drains connected to the bit lines and hold nonvolatile information. MCTr Ma and Mb control writing, erasure or reading of the information held in the Fg. A drive signal means 2 gives a drive signal to control gates(CG) of the MCTr. In a period wherein the drive signal is given to the CG of the MCTr, a bit line potential control means controls the potential of the bit lines so that they be changed in a prescribed rate. By this constitution, nonuniformity in threshold values of the memory cell transistors is held down and a multi-value memory is realized.</p> |
