发明名称 |
VIDEO SIGNAL PROCESSOR AND DISPLAY SYSTEM |
摘要 |
<p>PROBLEM TO BE SOLVED: To automatically adjust the sampling phase to an optimum value in the case of A/D-converting a video signal. SOLUTION: An input video signal VO representing a black/white level two- gradation test pattern is converted into 8-bit data at an A/D converter 4 synchronously with a sampling clock generated by a write control circuit 5 and the converted data are stored in a memory 6. An MPU 9 reads data of picture elements for a valid period of a video signal stored in the memory 6, calculates a difference AT between a mean value of white level picture element data larger than a prescribed value and a mean value of black level picture element data smaller than a prescribed value a sum VT between a variance of the white level picture element data and a variance of the black level picture element data and controls a phase of the sampling clock generated by the write control circuit 5 so as to maximize the AT and to minimize the VT.</p> |
申请公布号 |
JPH0946619(A) |
申请公布日期 |
1997.02.14 |
申请号 |
JP19950192097 |
申请日期 |
1995.07.27 |
申请人 |
HITACHI LTD |
发明人 |
NAKA KAZUTAKA;MARUYAMA ATSUSHI;URATA HIROYUKI;IWANAGA MASAO |
分类号 |
G06F1/10;G09G5/18;H03L7/081;H03L7/091;H03L7/199;H04N5/04;H04N5/12;H04N5/20;H04N5/66;H04N9/64;(IPC1-7):H04N5/66 |
主分类号 |
G06F1/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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