| 摘要 |
PROBLEM TO BE SOLVED: To improve development efficiency of a product by reducing the number of trial manufacture for estimating design/rule for minimizing a chip size within a producible range and readily set the order of priority for check items when a chip size is further reduced. SOLUTION: A circuit pattern formed on each wafer constituting a lot is made a contact hole pattern and a gate electrode pattern, both superposition misregistration and line width dispersion in photolithography are classified into a dispersion element among lots and a dispersion element in a lot and a distance between the contact hole 1 and the gate electrode 2 is regulated based on various parameters forming the elements. |
