发明名称 FILTER CIRCUIT
摘要 PROBLEM TO BE SOLVED: To suppress power consumption while realizing high speed initial synchronization by conducting initial synchronization with a matched filter and using a sliding correlation device to conduct correlation calculation thereby stopping power supply to the matched filter. SOLUTION: A peak detection circuit TH connecting to a post stage of a matched filter MF receiving an input signal detects plural timings when an output of the matched filter MF exceeds a prescribed level, and a controller CTRL 1 receiving an output signal sets a basic timing of multiplication in each of sliding correlation devices SC1-SC3. Furthermore, the input signal is given to the sliding correlation devices SC1-SC3 via switches SW2-SW4, a DLL circuit (synchronization tracing device) connecting to the post stage fine-adjusts a timing of multiplication based on outputs of the sliding correlation devices SC1-SC3 and the timing from the controller CTRL 1 and interrupts the operation of the matched filter MF after the detection of the timing.
申请公布号 JPH0946174(A) 申请公布日期 1997.02.14
申请号 JP19950215389 申请日期 1995.07.31
申请人 SHARP CORP;YOZAN:KK 发明人 SHU NAGAAKI;KOTOBUKI KOKURIYOU;KOU SHIYUCHIYOKU;YAMAMOTO MAKOTO
分类号 H03H17/02;H03H11/04;H04B1/709;H04J13/00;H04L7/00;H04L7/10 主分类号 H03H17/02
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