发明名称 VARIABLE DELAY CIRCUIT
摘要 PROBLEM TO BE SOLVED: To decrease a minimum adjustment unit of a delay time by using a time constant consisting of an inverter output resistor and a capacitor and a threshold level of an inverter of a next stage by connecting a switch and a capacitor between inverter stages. SOLUTION: (n+1) inverters 1 are connected in cascade and a series circuit consisting of a switch 2 and a capacitor 3 is connected respectively between connecting points of adjacent inverters and a common potential point. A binary code signal (control signal) S(M) representing number M(0<=M<=n) of the switches 2 closed simultaneously by a decoder 4 is decoded to control an optional number M of the switches 2 to be close and the remaining (n-M) switches respectively. Let a delay time depending on a time constantτ=RC consisting of an output resistor R of the inverter 1 and a capacitance C of the capacitor 3 and on a threshold level Vth at a rising of the input to the next stage inverter be Trc and let a propagation delay time of each inverter 1 be Tin, then the range of (n+1)Tin to (n+1)Tin+nTrc is adjusted by the minimum adjustment unit of Trc.
申请公布号 JPH0946195(A) 申请公布日期 1997.02.14
申请号 JP19950190541 申请日期 1995.07.26
申请人 ADVANTEST CORP 发明人 SAKAI HIDEO;OKAYASU TOSHIYUKI
分类号 G01R31/28;H03K5/13;H03K19/00;H03K19/0948;(IPC1-7):H03K5/13;H03K19/094 主分类号 G01R31/28
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