发明名称 |
Semiconductor disk system having a plurality of flash memories |
摘要 |
A NAND bus interface independently receives 16 ready/busy signals from 16 flash EEPROM chips and thereby separately manages the operating states of these flash EEPROMs. Once a flash EEPROM as a write access target is set in a ready state, a write access to this write access target flash EEPROM is started without waiting for completion of the operations of all the flash EEPROMs. Each flash EEPROM is of a command control type capable of automatically executing a write operation. This allows parallel processing of the flash EEPROMs, i.e., a write access to a given EEPROM can be performed while a data write to another flash EEPROM is being executed. An ECC calculating circuit calculates a data string transferred in units of 256 bytes from a data buffer by a processor, and generates an ECC corresponding to that data string. The 256-byte data string is added with the generated ECC and transferred to a data register of a flash EEPROM. Even if abnormal cells are produced at the same bit position in a plurality of pages of a flash EEPROM, only one abnormal cell is contained in a data string as an object of the ECC calculation. This makes it possible to perform error detection and correction by a common simple ECC calculation without using any complicated ECC arithmetic expression with a high data recovery capability.
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申请公布号 |
US5603001(A) |
申请公布日期 |
1997.02.11 |
申请号 |
US19950435854 |
申请日期 |
1995.05.05 |
申请人 |
KABUSHIKI KAISHA TOSHIBA |
发明人 |
SUKEGAWA, HIROSHI;MAKI, YASUNORI;INAGAKI, TAKASHI |
分类号 |
G06F3/06;G06F11/10;(IPC1-7):G06F12/00;G06F13/00 |
主分类号 |
G06F3/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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