| 摘要 |
A power-on detection circuit for detecting when a supply output voltage exceeds a predetermined level. According to a present embodiment, the power-on detection circuit generally comprises a pull-up transistor, a pull-down transistor, and an inverter. The pull-up transistor and the pull-down transistor are commonly coupled to a node for biasing the node to a first voltage, and the inverter has its input coupled to receive the first voltage. The inverter indicates that the supply output voltage is less than the predetermined level when the first voltage is greater than a trip voltage of the inverter. The inverter indicates that the supply output voltage exceeds the predetermined level when the first voltage is less than the trip voltage of the inverter. According to one embodiment, a biasing circuit comprising a voltage divider is provided to bias the pull-down transistor as a function of the supply output voltage such that the gate voltage of the pull-down transistor varies at the same rate as the supply output voltage.
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