| 摘要 |
A syncronous signal detecting circuit in a digital VCR is provided, which includes a clock generator 11 for detecting a serial clock SCLK entering from a VCR and converting it into a parallel clock PCLK, a signal controller 13 for generating a window signal for limiting a range for detecting a vertical sync signal using the parallel clock PCLK and a head switching signal, a sync detector 12 for detecting the vertical sync signal from serial data SD according to the window signal of the signal controller 13, a vertical sync compensation part 16 for dividing the head switching signal applied syncronized with a track including the vertical sync signal to generate the window signal only in corresponding track, and counting the horizontal sync signal when there is no vertical sync signal to create a window control signal for generating the vertical sync signal, a data converter 14 for converting serial data SD into parallel data PD according to the output PCLK of clock generator 11, and a delay 15 for adjusting the timing of the output PD of data converter 14 and output of sync detector 12 according to the output PCLK of clock generator 11.
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