| 摘要 |
A heapsort processor includes a first decoder for selecting a parent macro cell and a second decoder for selecting macro cell pair 480 having twice or twice plus one the address of the parent. The data of the parent is read to the first bit line, while data of a macro cell storing larger data in macro cell pair is read to the second bit line. The processor further includes a circuit for exchanging, when the data on the second bit line is larger than the data on the first bit line, the data of these bit lines and for writing the exchanged data to original macro cells. This enables generation of heap data. When a macro cell storing a root is selected by disabling the second decoder, part of a heapsort algorithm can be implemented in a hardware.
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