| 摘要 |
PROBLEM TO BE SOLVED: To attain display offset processing including line number conversion processing without increasing the memory capacity. SOLUTION: A synchronizing signal generating circuit 22 generates a correction synchronizing signal delaying a synchronizing signal based on a display vertical offset and line number conversion processing. A memory write control circuit 17 writes data based on a synchronizing signal on time basis to a frame memory 6. A memory read control circuit 21 reads the data based on a corrected synchronizing signal on time basis from the frame memory 6. Since the corrected synchronizing signal is delayed more than the synchronizing signal, even when a read rate is higher than a write rate, precedence of read over write is prevented. Thus, display offset processing including line number conversion processing is attained without increasing the memory capacity. |
