| 摘要 |
PROBLEM TO BE SOLVED: To provide a quotient selection circuit providing the capacity exactly and effectively calculating a sticky bit when a final partial remainder is negative, shortening the waiting time when a quotient selection rule is executed and having a minimum size and a division circuit including the same quotient selection circuit. SOLUTION: A quotient digit selection circuit has a 4-bit carry propagation adder 500 in which first to fourth sum bits and first to fourth carry bits are inputted and first to fourth predictive partial remainder bits are outputted, a 4-bit/zero detector 501 in which the first to fourth predictive partial remainder bits are inputted and an all/zero signal is formed, a 4-bit 1 detector 502 in which the first to fourth predictive partial remainer bits are inputted and an all/one signal is formed, a negative OR gate 503 in which a fifth sum bit and a fifth carry bit are inputted and a fifth bit/zero signal is formed and a zero circuit 504 in which the all/one signal, a fifth bit/zero signal and the all/zero signal are inputted and a zero output is formed. |
