| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide a clock generation circuit which can minimize the deterioration of velocity against a system clock CLK and also can reduce the power consumption and noises. SOLUTION: The clock generators 12, 20... are provided for the function blocks 14, 16... and operated by the control signals FCTL 14, 16... which control the operations of the corresponding function blocks respectively. Therefore, a clock generation circuit operates only when every function block has to operate and generates an internal clock. As the burden of every clock generator is reduced, there is no need to provide a clock buffer, etc. Thus the deterioration of velocity is never caused due to the clock buffer, etc. Furthermore, the current consumption and noises can be reduced since only a necessary clock generator operates as necessary in response to a control signal.</p> |
