| 摘要 |
PROBLEM TO BE SOLVED: To increase the operation voltage margin of a word line, ensure the specified value of data hold time, and cope with low voltage performance, regarding a dynamic memory wherein a dynamic cell is constituted of a capacitor and a transistor. SOLUTION: A gate electrode 45 of an nMOS transistor 40 as a cell transistor is constituted of a P-type poly silicon layer. The amount of ion implantation of boron B for threshold voltage adjustment, which boron is implanted in a region for forming the nMOS transistor 40, is reduced. As the threshold voltage when '0' data are stored, the conventional threshold voltage is ensured, and the back bias dependence coefficient is reduced. |
