| 摘要 |
PROBLEM TO BE SOLVED: To improve the PLL characteristic. SOLUTION: The circuit is provided with a register 361 receiving data designating a group and a channel, frequency divider circuits 351-355 frequency- dividing an oscillation signal S30 with a prescribed frequency into plural different frequencies, a selector circuit 356 extracting selectively a frequency division signal Sx with a prescribed frequency among plural frequencies according to data b1, b0 designating a group among data fed to the register 361, and a conversion circuit 362 converting data b6-b2 designating a channel among data fed to the register 361 into data for a frequency division ratio N for a variable frequency divider circuit 311 of a PLL 31. The frequency division signal Sx is fed to a phase comparator circuit 313 of the PLL 31 as a reference frequency signal and data of conversion result of the conversion circuit 362 are set to a variable frequency divider circuit 311 as frequency division ratio data. |
