| 摘要 |
<p>PROBLEM TO BE SOLVED: To reduce a memory capacity required for a program by improving the utilizing efficiency of a conventional register in the microcomputer. SOLUTION: A CPU 1-1 is provided with a zero register 1-12 being a zero data read exclusive register for the CPU 1-1 as an addressing means having an address space where upper and lower limits of addresses are consecutive, allocating a 32k-byte built-in ROM 1-2, a 2k-byte built-in RAM 1-3, each of peripheral circuits 1-4-1-1-4-3 to a specific address of the address space for accessing, a code expansion means 1-12 expanding 16-bit data (disp) 1-6 used to designate an instruction up to a bit width corresponding to the address space by a code bit signal, and a 32-bit adder 1-7 receiving an output of the code expansion means 1-12 and the zero register 1-12 and providing an output of a specific address 1-8.</p> |
