| 摘要 |
PROBLEM TO BE SOLVED: To easily and exactly detect and hold the timing of arbitrary and plural interrupting requests. SOLUTION: Plural interrupting request signals A-D are latched by correspondent interruption latch registers 1A-1D. By writing a high-level signal into any prescribed one of condition selecting registers 2A-2D, any prescribed one of outputs from the interruption latch registers 1A-1D is outputted through AND circuits 3A-3D to an OR circuit 4. The edge of the signal outputted from the OR circuit 4 to be changed from the low level to the high level is detected by an edge detection circuit 5 and when a pulse generated at detection timing is inputted to a count value holding register 6, the count value holding register 6 holds the count value of a counter 7 at that time. |
